Reducing Peak Power Consumption inMulti-Core Systems without ViolatingReal-Time Constraints
Reducing Peak Power Consumption inMulti-Core Systems without ViolatingReal-Time Constraints
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DOI：
10.1109/tpds.2013.131
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发表时间：
2014-04
影响因子：
5.3
通讯作者：
Jinkyu Lee;B. Yun;K. Shin
中科院分区：
文献类型：
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作者：
Jinkyu Lee;B. Yun;K. Shin
多核芯片以低成本实现高性能和可靠性的潜力使其成为嵌入式实时系统的理想计算平台。因此，多核芯片的电源管理已成为嵌入式实时系统设计中的一个重要问题。大多数现有的方法已经被设计为调节平均功耗的行为，例如最小化总能耗或芯片温度。然而，很少有人关注芯片上瞬时功耗的最坏情况行为，称为芯片级峰值功耗，这是一个重要的设计参数，决定了芯片设计/封装和底层电源的成本和/或大小。我们通过在设计时降低芯片级峰值功耗而不违反任何实时约束来解决这个问题。我们通过仔细调度实时任务来实现这一点，而不依赖于任何额外的硬件实现电源管理，如动态电压和频率缩放。具体来说，我们提出了一种新的调度算法FPΘ，限制并发执行的任务分配在不同的核心，并进行了可并行性分析。使用这种分析，我们开发了一种方法，找到一组并发的可执行任务，使设计时芯片级的峰值功耗最小化，并满足所有的时序要求。我们通过仿真表明，所提出的方法不仅保持设计时芯片级的峰值功耗低至理论下限的平凡的情况下，但也降低了峰值功耗的非平凡的情况下，高达12.9%的情况下，没有限制并发任务执行。
The potential of multi-core chips for high performance and reliability at low cost has made them ideal computing platforms for embedded real-time systems. As a result, power management of a multi-core chip has become an important issue in the design of embedded real-time systems. Most existing approaches have been designed to regulate the behavior of average power consumption, such as minimizing the total energy consumption or the chip temperature. However, little attention has been paid to the worst-case behavior of instantaneous power consumption on a chip, called chip-level peak power consumption, an important design parameter that determines the cost and/or size of chip design/packaging and the underlying power supply. We address this problem by reducing the chip-level peak power consumption at design time without violating any real-time constraints. We achieve this by carefully scheduling real-time tasks, without relying on any additional hardware implementation for power management, such as dynamic voltage and frequency scaling. Specifically, we propose a new scheduling algorithm FPΘ that restricts the concurrent execution of tasks assigned on different cores, and perform its schedulability analysis. Using this analysis, we develop a method that finds a set of concurrent executable tasks, such that the design-time chip-level peak power consumption is minimized and all timing requirements are met. We demonstrate via simulation that the proposed method not only keeps the design-time chip-level peak power consumption as low as the theoretical lower bound for trivial cases, but also reduces the peak power consumption for non-trivial cases by up to 12.9 percent compared to the case of no restriction on concurrent task execution.