A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2
A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2
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DOI：
10.1109/hpsr.2009.5307432
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发表时间：
2009-06
期刊：
影响因子：
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通讯作者：
Shan Gao;T. Kihara;S. Shimizu;Y. Arakawa;N. Yamanaka;Akifumi Watanabey
中科院分区：
文献类型：
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作者：
Shan Gao;T. Kihara;S. Shimizu;Y. Arakawa;N. Yamanaka;Akifumi Watanabey
本文提出了一种新的流量工程方法，使用片上立体网络，由虚拟节点和虚拟链路。立体模型网络在可重构处理器DAPDNA-2上实现。近年来，为了保证服务质量，流量工程得到了广泛的研究.该建议是一个实验性的解决方案与片上立体网络，其中虚拟链路和虚拟节点构造的一些PE（处理元件）。我们通过虚拟数据包在片上立体模型网络上交换的行为来获得真实的流量波动。在本文中，作为第一次尝试，以实现我们的最终目标，我们实现了立体模型网络和确定基本路径计算，其中这两个功能是我们的算法的基本功能。立体模型网络流量工程可以实现更复杂的网络设计，如自适应流量平衡或多度量设计。
This paper proposes a novel traffic engineering method using on-chip diorama network that consists of virtual nodes and virtual links. The diorama network is implemented on reconfigurable processor DAPDNA-2. In these years, traffic engineering has widely researched to guarantee QoS (Quality of Service). The proposal is an experimental solution with the onchip diorama network, where virtual links and virtual nodes are constructed by some PEs (processing elements). We obtain the realistic traffic fluctuation through the behavior of virtual packets exchanged on the on-chip diorama network. In this paper, as first trial to achieve our final goal, we implemented diorama network and confirmed basic path calculation, where both functions are an essential function of our algorithm. The diorama network traffic engineering can realize more sophisticated network design like adaptive traffic balancing or multi-metric design.