9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS
9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS
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采用 65nm CMOS 封装的 9.6 A 1.3mW 0.6V WBAN 兼容子采样 PSK 接收器
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
A. Natarajan
中科院分区：
文献类型：
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作者：
Jiao Cheng;Nan Qi;P. Chiang;A. Natarajan
IEEE802.15.6标准的发布引起了人们对用于无线体域网（WBAN）的低功耗技术的兴趣。功耗、电源电压和IC面积是成功实现WBAN的一些最重要的标准。模拟密集型外差接收机（RX）之前已经过演示，由于IF处存在面积密集型模拟构建模块（如低通滤波器），1至1.2V电源功耗为4至5 mW，同时占用较大的硅面积[1，2]。数字密集型RX架构可能会导致低于1V的工作电压，从而显著降低功耗和面积，但需要系统和电路级创新才能实现所需的灵敏度和线性度。本文介绍了一种全数字化的2.4GHz RX架构，该架构采用了带数字IF/基带信号处理的子采样技术，实现了低功耗（1.3mW）和低电压（0.6V）工作，从而将功耗降低了约3倍。早期的模数转换导致IC仅占用0.35mm2的有源硅面积。虽然该IC专注于WBAN解调，但所提出的技术也适用于其他低功耗标准。
The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBAN). The power dissipation, supply voltage, and IC area are some of the most important criteria for successful WBAN implementations. Analog-intensive heterodyne receivers (RX) have been previously demonstrated, consuming 4 to 5mW of power from a 1-to-1.2V supply while occupying large silicon area, due to the presence of area-intensive analog building blocks such as low-pass filters at the IF [1,2]. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in power consumption and area, but require system and circuit-level innovations to achieve desired sensitivity and linearity. This paper presents a mostly-digital 2.4GHz RX architecture that uses a sub-sampling technique with digital IF/baseband signal processing to enable low-power (1.3mW) and low-voltage (0.6V) operation, resulting in ~3x reduction in power consumption. Early analog-to-digital conversion leads to the IC occupying only 0.35mm2 of active silicon area. While the IC focuses on WBAN demodulation, the presented techniques are applicable to other low-power standards as well.