An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration

An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration
复制标题

DOI：
10.1109/isscc.2007.373495
复制
发表时间：
2007-06
期刊：
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
影响因子：
--
通讯作者：
Cheng-Chung Hsu;Fong-Ching Huang;Chih-Yung Shih;Chen-Chih Huang;Ying-Hsi Lin;Chao-Cheng Lee;B. Razavi
Cheng-Chung Hsu;Fong-Ching Huang;Chih-Yung Shih;Chen-Chih Huang;Ying-Hsi Lin;Chao-Cheng Lee;B. Razavi
中科院分区：
其他
文献类型：
--
作者：
Cheng-Chung Hsu;Fong-Ching Huang;Chih-Yung Shih;Chen-Chih Huang;Ying-Hsi Lin;Chao-Cheng Lee;B. Razavi

文献摘要

被引文献

相似文献

采用90 nm CMOS工艺实现了一个11 B 800 MS/S时间交错ADC，可用于10 GBase-T应用。使用共源共栅源极跟随器的单个开环T/H电路实现了高分辨率和转换速率。失调和增益失配通过数字背景校准来校正。实测DNL <0.5LSB，INL <1.6LSB。在15和400 MHz输入下，实测SNDR分别为58和54 dB。1.4mm2 ADC采用1.3V电源供电时功耗为350 mW（T/H为1.5V）。
An 11 b 800MS/S time-interleaved ADC is implemented in a 90nm CMOS process for a 10GBase-T application. A single open-loop T/H circuit using a cascode source follower achieves high resolution and conversion rate. The offset and gain mismatches are corrected by the digital background calibration. The measured DNL and INL are <0.5LSB and <1.6LSB, respectively. The measured SNDRs are 58 and 54dB for 15 and 400MHz inputs, respectively. The 1.4mm2 ADC consumes 350mW from a 1.3V supply (1.5V for T/H).