The ACADIA ASIC: detector control and digitization for the Wide-Field Infrared Survey Telescope (WFIRST)
The ACADIA ASIC: detector control and digitization for the Wide-Field Infrared Survey Telescope (WFIRST)
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ACADIA ASIC：广域红外巡天望远镜 (WFIRST) 的探测器控制和数字化
DOI：
10.1117/12.2313067
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发表时间：
2018
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影响因子：
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通讯作者：
D. Content
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作者：
M. Loose;Brian S. Smith;G. Alkire;A. Joshi;D. Kelly;E. Siskind;S. Mann;J. Chen;A. Askarov;Joseph R. Fox;Edward Leong;A. Goodwin;D. Lindsay;D. Rossetti;Jonathan Mah;E. Cheng;L. Miko;H. Culver;Edward J. Wollack;D. Content
美国宇航局的宽视场红外巡天望远镜（WFIRST）项目开发了ACADIA ASIC，这是下一代探测器控制和采集系统芯片。该ASIC的目的是解决在航天器环境中操作低温探测器的严格要求。关键性能标准是在150 K至180 K温度范围内实现低模拟噪声和低功耗，同时支持传感器的全动态范围。ASIC主要用于操作WFIRST的Teledyne H4 RG，但其设计具有相当大的灵活性，可与大量其他探测器兼容。最多可并行处理40个模拟传感器输出，每个信号由具有可编程增益和带宽的低噪声前置放大器放大和调节，然后由16位逐次逼近模数转换器（ADC）数字化。ASIC包括24个模拟输出通道，可配置为可编程电压或电流源，用于为检测器生成偏置和参考。易于编程的序列器为检测器和ASIC内部电路提供定时控制，并可选择使用嵌入式微处理器进行更精细的读出方案。本文介绍了ACADIA ASIC设计的概况，详细描述了其模拟、混合信号和数字电路模块。ACADIA ASIC的第一个原型已经制造，功能和性能的初步测试结果已经测量。我们讨论了测试环境和获得的结果，并通过描述项目的后续步骤得出结论。ACADIA ASIC旨在操作Teledyne H4RG红外混合探测器（WFIRST宽场仪器的当前基准），但其设计具有相当大的灵活性，可与大量其他探测器兼容。每个模拟传感器输出由具有可编程增益和带宽的低噪声前置放大器放大和调节，然后由16位逐次逼近模数转换器（ADC）数字化。最多可并行处理40个信号。每个通道都提供一些基本的数学函数，如求和、求平均值、阈值比较和数字增益。此外，ASIC包括24个模拟输出通道，可配置为可编程电压或电流源，用于为检测器提供偏置和参考。整体时序控制由一个灵活但易于编程的序列器提供，可选择微处理器控制以实现更精细的读出方案。进一步的数字功能包括直接存储器访问（DMA）引擎、定时器、串行外设接口（SPI）和用于传输的科学数据格式化。所有的电路都受到保护，免受电离辐射的单粒子效应。我们将讨论开发工作的状态，重点是性能要求、一般设计特性和可用的测试结果。在开发过程中，已经构建了几个测试芯片，这些芯片已经证明与以前的解决方案相比，模拟性能有了显着改进，并且符合低温和室温操作的关键WFIRST要求。完整的40通道ACADIA ASIC原型已经制造完成，目前正在测试中。除了芯片本身，封装方法，测试环境和控制电子与计算机采集将被提出。
NASA's Wide-Field Infrared Survey Telescope (WFIRST) project has developed the ACADIA ASIC, a next generation detector control and acquisition system-on-a-chip. The purpose of this ASIC is to address the stringent requirements of operating a cryogenic detector in a spacecraft environment. Key performance criteria are low analog noise and low power consumption at temperatures between 150K and 180K while supporting the full dynamic range of the sensor. The ASIC is primarily intended to operate the Teledyne H4RG for WFIRST, but has been designed with considerable flexibility to provide compatibility with a large selection of other detectors. Up to 40 analog sensor outputs can processed in parallel, where each signal is amplified and conditioned by a low-noise pre-amplifier with programmable gain and bandwidth, and then digitized by a 16-bit successive approximation analog-to-digital converter (ADC). The ASIC includes 24 analog output channels that can be configured as programmable voltage or current sources, and are used to generate biases and references to the detector. A simple-to-program sequencer provides timing control for the detector and the ASIC internal circuits, with the option of using an embedded microprocessor for more elaborate readout schemes. This paper presents an overview of the ACADIA ASIC design with detailed descriptions of its analog, mixedsignal, and digital circuit blocks. First prototypes of the ACADIA ASIC have been fabricated, and preliminary test results of functionality and performance have been measured. We discuss the test environment and the obtained results, and conclude by describing the next steps for the project. The ACADIA ASIC is intended to operate the Teledyne H4RG infrared hybrid detector (current baseline for the WFIRST Wide-Field Instrument), but has been designed with considerable flexibility to provide compatibility with a large selection of other detectors. Each analog sensor output is amplified and conditioned by a low-noise pre-amplifier with programmable gain and bandwidth, and then digitized by a 16-bit successive approximation analog-to-digital converter (ADC). Up to 40 signals can be processed in parallel. Some basic math functions like summing, averaging, threshold comparison, and digital gain are available per channel. In addition, the ASIC includes 24 analog output channels that can be configured as programmable voltage or current sources, and are used to provide biases and references to the detector. Overall timing control is provided by a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes. Further digital capabilities include Direct Memory Access (DMA) engine, timers, Serial Peripheral Interface (SPI), and science data formatting for transmission. All circuitry has been protected against single event effects from ionizing radiation. We will discuss the status of the development effort, with focus on the performance requirements, general design features, and available test results. Over the course of the development, several test chips have been built that have already demonstrated significant improvements in analog performance over prior solutions, and have shown compliance with key WFIRST requirements for both cryogenic and room temperature operation. Prototypes of the full 40-channel ACADIA ASIC have been fabricated and are currently being tested. In addition to the chip itself, the packaging approach, test environment, and control electronics with computer acquisition will be presented.