A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms
A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms
复制标题
DOI：
--
复制
发表时间：
2011-06
期刊：
影响因子：
--
通讯作者：
Meng-Fan Chang;Wei-Cheng Wu;Chih-Sheng Lin;P. Chiu;Ming-Bin Chen;Yen-Huei Chen;H. Lai;Zhe-Hui Lin;S. Sheu;T. Ku;H. Yamauchi
中科院分区：
文献类型：
--
作者：
Meng-Fan Chang;Wei-Cheng Wu;Chih-Sheng Lin;P. Chiu;Ming-Bin Chen;Yen-Huei Chen;H. Lai;Zhe-Hui Lin;S. Sheu;T. Ku;H. Yamauchi
这项工作展示了第一个基于TSV的芯片到芯片键合堆叠层数可扩展的3D-SRAM宏。该3D-SRAM采用半主从（SMS）结构和自定时差分TSV信号传输（STDT）方案，以1）在各种层配置上提供恒定负载逻辑SRAM接口; 2）抑制TSV引起的功率和速度开销; 3）容忍管芯间变化;以及4）实现预键合KGD排序，以提高通用存储器容量平台的速度和良率。在具有层可扩展测试模式的制造的3D-SRAM宏中证明了以小的速度开销增加堆叠层数量的上级可扩展性。这个宏有两个SRAM层，通过最后通孔工艺和管芯到管芯键合堆叠。
This work demonstrates the first fabricated TSV-based die-to-die bonding stacked-layer-number-scalable 3D-SRAM macro. This 3D-SRAM uses a semi-master-slave (SMS) structure and a self-timed differential-TSV signal transfer (STDT) scheme to 1) provide a constant-load logic-SRAM interface across various layer configurations; 2) suppress TSV-induced power and speed overheads; 3) tolerate die-to-die variation, and 4) enable pre-bonding KGD sorting, to improve the speed and yield of universal-memory-capacity platforms. Superior scalability of increasing stacked layer number with small speed overheads is demonstrated in the fabricated 3D-SRAM macro with layer-scalable test-modes. This macro has two SRAM layers that are stacked by a via-last process with die-to-die bonding.