Developing dynamic profiling and debugging support in OpenCL for FPGAs
Developing dynamic profiling and debugging support in OpenCL for FPGAs
复制标题
在 OpenCL 中为 FPGA 开发动态分析和调试支持
DOI：
10.1145/3061639.3062230
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
Wu
中科院分区：
文献类型：
--
作者：
Anshuman Verma;Huiyang Zhou;S. Booth;Robbie King;J. Coole;A. Keep;John Marshall;Wu
随着 FPGA 逐渐成为一种有前景的通用计算加速器，软件开发人员迫切需要能够使用它们。 FPGA OpenCL 编译器的最新进展为从 OpenCL 内核代码合成 FPGA 硬件铺平了道路。为了更广泛地采用这种范式，仍然存在重大挑战。本文介绍了我们在 OpenCL 中为 FPGA 开发动态分析和调试支持方面所做的努力。我们首先提出原始代码模式，包括时间戳和事件排序函数，然后开发一个可以轻松插入 OpenCL 内核的框架，以动态收集和处理运行时信息。
With FPGAs emerging as a promising accelerator for general-purpose computing, there is a strong demand to make them accessible to software developers. Recent advances in OpenCL compilers for FPGAs pave the way for synthesizing FPGA hardware from OpenCL kernel code. To enable broader adoption of this paradigm, significant challenges remain. This paper presents our efforts in developing dynamic profiling and debugging support in OpenCL for FPGAs. We first propose primitive code patterns, including a timestamp and an event-ordering function, and then develop a framework, which can be plugged easily into OpenCL kernels, to dynamically collect and process run-time information.