Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's
Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's
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0.1-的设计与实验技术
DOI：
10.1109/edl.1987.26695
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发表时间：
1987
影响因子：
4.9
通讯作者：
R. Dennard
中科院分区：
文献类型：
--
作者：
G. Sai;M. Wordeman;D. Kern;É. Ganin;S. Rishton;D. Zicherman;H. Schmid;M. Polcari;H. Ng;P. Restle;T. Chang;R. Dennard
第一批器件性能结果来自旨在评估0.1-µm栅长区域内FET技术可行性的实验。针对这些尺寸的低温器件设计考虑导致了0.15-V阈值和0.6-V电源，采用正向偏置衬底。采用直写式电子束曝光法，在所有水平上制作了自对准的、几乎完全规模化的器件和简单的电路，栅长低至0.07µm，测试的器件特性超过了750ms/mm，这是迄今为止在SiFET中获得的最高值。
The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 µm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FET's.