A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance
复制标题
脉动神经 CPU 处理器将深度学习和通用计算与增强的数据局部性和端到端性能相结合
DOI：
10.1109/jssc.2022.3214170
复制
发表时间：
2023
影响因子：
5.4
通讯作者：
Gu, Jie
中科院分区：
文献类型：
--
作者：
Ju, Yuhao;Gu, Jie
虽然神经网络（NN）加速器近年来得到了显着发展，但CPU仍然是常用异构架构中加速器的数据管理和预/后处理所必需的，该架构通常包含NN加速器和处理器核心，数据传输由直接存储器访问（DMA）引擎执行。这项工作提出了一种特殊的神经处理器，称为收缩神经CPU处理器（SNCPU），它是一种统一的架构，结合了深度学习和通用计算，用于第五代精简指令集计算机（RISC-V），以提高机器学习（ML）任务的端到端性能。SNCPU具有64%-80%的处理元件（PE）逻辑重用和10%的面积开销，可以配置为10个RISC-V CPU核心。为了提高深度神经网络（DNN）加速器的利用率，消除现有异构架构中CPU和DNN加速器之间昂贵的数据传输，开发了专用的双向并行和四种不同的工作模式。制造了一个65 nm的测试芯片，在ImageNet、Cifar 10和MNIST数据集的端到端图像分类任务上表现出39%-64%的性能提升，PE利用率超过95%，功率效率高达1.8TOPs/W。
While neural network (NN) accelerators are being significantly developed in recent years, CPU is still essential for data management and pre-/post-processing of accelerators in a commonly used heterogeneous architecture, which usually contains an NN accelerator and a processor core with data transfer performed by direct memory access (DMA) engine. This work presents a special neural processor, referred to as a systolic neural CPU processor (SNCPU), which is a unified architecture combining deep learning and general-purpose computing for fifth-generation of reduced instruction set computer (RISC-V) to improve end-to-end performance for machine learning (ML) tasks compared with a common heterogeneous architecture with CPU and accelerator. With 64%–80% processing elements (PEs) logic reuse and 10% area overhead, SNCPU can be configured into ten RISC-V CPU cores. Special bi-directional dataflow and four different working modes are developed to enhance the utilization of deep NN (DNN) accelerator and eliminate the expensive data transfer between CPU and DNN accelerator in existing heterogeneous architecture. A 65-nm test chip was fabricated demonstrating a 39%–64% performance improvement on end-to-end image classification tasks for ImageNet, Cifar10, and MNIST datasets with over 95% PE utilization and up to 1.8TOPs/W power efficiency.
登录
查看更多内容
影响因子：
5.4
作者：
Jingcheng Wang;Xiaowei Wang;Charles Eckert;Arun K. Subramaniyan;R. Das;D. Blaauw;D. Sylvester
通讯作者：
Jingcheng Wang;Xiaowei Wang;Charles Eckert;Arun K. Subramaniyan;R. Das;D. Blaauw;D. Sylvester
SamurAI：1.7MOPS-36GOPS 自适应多功能物联网节点，具有 15,000× 峰值至空闲功耗降低、207ns 唤醒时间和 1.3TOPS/W ML 效率
DOI：
--
发表时间：
2020
期刊：
2020 IEEE Symposium on VLSI Circuits
影响因子：
--
作者：
I. Panades;Benoît Tain;J. Christmann;David Coriat;R. Lemaire;C. Jany;B. Martineau;F. Chaix;A. Quelen;Emmanuel Pluchart;J. Noel;R. Boumchedda;A. Makosiej;Maxime Montoya;Simone Bacles;David Briand;Jean;A. Valentian;Frédéric Heitzmann;E. Beigné;F. Clermidy
通讯作者：
F. Clermidy
A%2065nm%20Systolic%20Neural%20CPU%20Processor%20for%20Combined%20Deep%20Learning%20and%20General-Purpose%20Computing%20with%2095%%20PE%20Utilization,%20High%20Data%20Locality%20and%20Enhanced%20End-
DOI：
10.1109/isscc42614.2022.9731757
发表时间：
2022
期刊：
International Solid-State Circuit Conference
影响因子：
--
作者：
Ju, Yuhao;Gu, Jie
通讯作者：
Gu, Jie
1.15 TOPS/W、16 核并行超低功耗集群，具有 2b 至 32b 完全灵活的位精度和矢量锁步执行模式
DOI：
--
发表时间：
2021
期刊：
European Solid-State Circuits Conference
影响因子：
--
作者：
Angelo Garofalo;G. Ottavi;Alfio Di Mauro;Francesco Conti;Giuseppe Tagliavini;L. Benini;D. Rossi
通讯作者：
D. Rossi
原型 AR/VR 硬件的系统级设计和集成，采用 7nm 技术的定制低功耗 DNN 加速器芯片，用于编解码器化身
DOI：
--
发表时间：
2022
期刊：
IEEE Custom Integrated Circuits Conference
影响因子：
--
作者：
H. Sumbul;Tony F. Wu;Yuecheng Li;Syed Shakib Sarwar;W. Koven;Eli Murphy;Xingxing Cai;E. Ansari;D. Morris;Huichu Liu;Doyun Kim;E. Beigné
通讯作者：
E. Beigné