Floorplanning and signal assignment for silicon interposer-based 3D ICs
Floorplanning and signal assignment for silicon interposer-based 3D ICs
复制标题
基于硅中介层的 3D IC 的布局规划和信号分配
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Ting
中科院分区：
文献类型：
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作者：
Wen;M. Chang;Ting
基于中介层的3D IC（或称为2.5D IC）已被视为真正的3D堆叠IC的替代方法，其将多个裸片安装在硅中介层上，并通过中介层中的互连在裸片之间路由信号。然而，插入器上的管芯的布图规划以及宏凸块和TSV的信号分配将在很大程度上影响2.5D IC中的互连的线长。由于长互连线会降低2.5D集成电路的性能，因此2.5D集成电路的多芯片布图规划问题和信号分配问题是关键。针对2.5D集成电路中的多芯片布图规划和信号分配问题，分别提出了基于枚举的算法和基于网络流的算法。此外，为了加快布图规划和信号分配算法，提出了几种加速技术。实验结果表明，该方法可以有效地减少2.5D集成电路中的总线长，加速技术可以显着提高算法的速度。
Interposer-based 3D ICs (or known as 2.5D ICs) have been seen as an alternative approach to true 3D stacked ICs, which mount multiple dies on a silicon interposer and route signals between dies by the interconnects in the interposer. However, the floorplan of dies on the interposer and the signal assignment for macro-bumps and TSVs will largely impact the wirelength of the interconnects in a 2.5D IC. Because long interconnects would degrade the performance of 2.5D ICs, the multi-die floorplanning problem and signal assignment problem for 2.5D ICs are critical. This paper presents an enumeration-based algorithm and a network-flow-based algorithm to solve the multi-die floorplanning and signal assignment problems in a 2.5D IC, respectively. Also, to speed up the floorplanning and signal assignment algorithms, several acceleration techniques are proposed. The experimental results reveal that this work can effectively reduce the total wirelength in a 2.5D IC and the acceleration techniques can significantly speed up the proposed algorithms.