A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures
A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures
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高吞吐量非二进制 LDPC 解码器调查：ASIC、FPGA 和 GPU 架构
DOI：
10.1109/comst.2021.3126127
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发表时间：
2021
影响因子：
35.6
通讯作者：
Falcao, G.
中科院分区：
文献类型：
--
作者：
Ferraz, O.;Subramaniyan, S.;Chinthalaa, R.;Andrade, J.;Cavallaro, J. R.;Nandy, S. K.;Silva, V.;Zhang, X.;Falcao, G.
当码字长度中等或信道存在突发错误时，非二进制低密度奇偶校验码比二进制低密度奇偶校验码具有更高的纠错性能。未来数字通信对高速解码器的需求导致了对优化的NB-LDPC解码算法和高效实现的研究，目标是高吞吐量和低能耗水平。我们对现有的NB-LDPC解码硬件进行了全面的调查，以优化这些参数。尽管现有的NB-LDPC解码器在计算复杂度和内存需求方面进行了优化，但在吞吐量、功耗和面积优化方面仍然落后于二进制解码器。本研究有助于全面了解基于特定应用的集成电路（ASIC）、现场可编程门阵列（FPGA）和图形处理单元（GPU）系统的最新技术，并强调了在实现更高效的NB-LDPC解码器架构的道路上仍需克服的当前挑战。
Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.