Throughput enhancement strategy of maskless electron beam direct writing for logic device
Throughput enhancement strategy of maskless electron beam direct writing for logic device
复制标题
逻辑器件无掩模电子束直写产能提升策略
DOI：
10.1109/iedm.2000.904446
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发表时间：
2000
期刊：
影响因子：
--
通讯作者：
T. Kuroda
中科院分区：
文献类型：
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作者：
R. Inanami;S. Magoshi;S. Kousai;M. Hmada;T. Takayanagi;K. Sugihara;K. Okumura;T. Kuroda
提出了一种用于逻辑器件中半导体电路的图形设计方法，该方法实现了具有足够吞吐量的电子束曝光。通过去除可用的标准单元（SC），可以通过重复逻辑合成和P和R（布局和布线）来减少EB照射的数量。该设计方法仅用17个SC就可以生成一个约140 kGates的功能块，用24个SC就可以实现最少的EB发射次数。SC的总面积和芯片的功耗仅增加了10%。
A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P and R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.