Invalid state identification for sequential circuit test generation
Invalid state identification for sequential circuit test generation
复制标题
时序电路测试生成的状态识别无效
DOI：
10.1109/ats.1996.555128
复制
发表时间：
1996
期刊：
影响因子：
--
通讯作者：
Jwu
中科院分区：
文献类型：
--
作者：
Hsing;Chung;Jwu
对于时序电路测试码的生成，无效状态的信息将对后向调整有很大的帮助，从而减少测试生成时间。针对时序电路测试生成问题，提出了三种发现无效状态的算法。前两种算法分别通过搜索所有有效状态和可达状态来搜索无效状态的完整集合。第一种算法对于无效状态多于有效状态的电路是有效的，而第二种算法对于具有比无效状态更多的有效状态的电路是有效的。第三种算法只搜索测试生成所需的无效状态，以便提前停止调整。在ISCAS基准电路上的实验结果表明，该算法可以在短时间内识别无效状态，并在故障覆盖率、检测效率和生成时间方面帮助显著提高测试生成。
For sequential circuit test pattern generation, the information on invalid states will help greatly on backward justification to reduce the test generation time. This paper proposes three algorithms to find invalid states for sequential circuit test generation. The first two algorithms search the complete set of invalid states by exploring all valid states and reachable states respectively. The first algorithm is efficient for circuits having more invalid states than valid states while the second algorithm is efficient for circuits having more valid states than invalid states. The third algorithm searches only the invalid states that are required for test generation to stop justification early. Experimental results on ISCAS benchmark circuits show that the algorithm can identify invalid states in short time and can help improve test generation significantly in the fault coverage, detection efficiency, and generation time.