Feasibility of plasmonic circuits for on-chip interconnects
Feasibility of plasmonic circuits for on-chip interconnects
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DOI：
10.1016/j.sse.2019.03.066
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发表时间：
2019-06-01
影响因子：
1.7
通讯作者：
Ota, M.
中科院分区：
文献类型：
--
作者：
Fukuda, M.;Tonooka, Y.;Ota, M.
提出了利用互补金属氧化物半导体（CMOS）兼容工艺制作等离子体激元电路的可行性，并从工作速度和能量损耗的角度对电路性能进行了数值和实验讨论。等离子体激元信号的传输速度，这是由电路的色散，计算为约两个数量级高于电信号。使用散粒噪声限制估计每单个传输比特的能量损失，并且澄清了如果传输距离被设置为几百微米内的区域，则等离子体信号上级电信号。基于这些结果和各个等离子体元件的实验结果，证明了等离子体电路的可行性。此外，等离子体电路，如波分复用网络的功能扩展的可行性，讨论了使用CMOS兼容工艺制造的等离子体元件的实验值。这些等离子体电路和网络可以使用CMOS兼容工艺合并到硅衬底上的硅集成电路中。
Feasibility of fabricating plasmonic circuits by complementary metal-oxidesemiconductor (CMOS) compatible processes is presented, and the circuit performances are numerically and experimentally discussed from the viewpoint of operating speed and energy loss. The transmission speed of plasmonic signals, which is governed by the dispersion of circuits, is calculated to be about two orders of magnitude higher than that of electric signals. The energy loss per single transmitted-bit is estimated using shot-noise limits, and it is clarified that plasmonic signals are superior to electric ones if the transmitted distance is set to an area within a few hundred micrometers. Based on these results and the experimental results of each plasmonic components, the feasibility of plasmonic circuits are demonstrated. In addition, the feasibility of the functional expansion of plasmonic circuits, such as wavelength-division-multiplexing networks, is discussed using experimental values of plasmonic components fabricated by CMOS-compatible processes. These plasmonic circuits and networks can be merged into silicon integrated circuits on a silicon substrate using CMOS compatible processes.