Analysis and Design of an 8.5-Gb/s/link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers

Analysis and Design of an 8.5-Gb/s/link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers
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使用能量均衡传输线耦合器的 8.5 Gb/s/链路多点总线的分析和设计

DOI:
10.1109/tcsi.2015.2437515
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发表时间:
2015
期刊:
IEEE Transactions on Circuits and Systems-I: Regular Papers
影响因子:
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通讯作者:
Tadahiro Kuroda
Tadahiro Kuroda
中科院分区:
--
文献类型:
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作者:
Atsutake Kosuge;Shu Ishizuka;Masao Taguchi;Hiroki Ishikuro;Tadahiro Kuroda

文献摘要

相似文献

提出了一种 8.5 Gb/s/链路非接触式多点总线。通过在每个信号分支点使用传输线耦合器,可以显着减少限制传统多点总线接口数据速率的信号反射。由于能量均衡技术为每个端口提供相同的信号电平,因此可以实现更宽的接收器余量。与最先进的多点总线接口相比,数据速率提高了1.8倍。本文讨论了能量均衡传输线耦合器的理论分析和设计技术。通过使用全 3D EM 模拟器进行的模拟以及使用 FR4 测试板进行的实验,验证了设计方法。由于耦合器的低切特性,低频分量被截止,使得微分脉冲到达接收器输入点。接收器通过使用迟滞特性对接收到的脉冲进行积分来检测并恢复它们。本文还讨论了传输线耦合器收发器的设计技术。使用90 nm CMOS工艺制造的测试芯片验证了所提出的方法。对八点多点总线系统原型进行的实验证实数据速率为 8.5 Gb/s/链路。在 BER 为 10-12 时,测得的远端模块的时序余量为 0.49-UI。电源电压为 1.2V 时,收发器的功耗为 75.6mW。
An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V.