DRAM Yield Analysis and Optimization by a Statistical Design Approach
DRAM Yield Analysis and Optimization by a Statistical Design Approach
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通过统计设计方法进行 DRAM 良率分析和优化
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
D. Schmitt
中科院分区：
文献类型：
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作者：
Yan Li;Helmut Schneider;F. Schnabel;R. Thewes;D. Schmitt
本文通过统计方法研究了 DRAM 核心电路的电产率，该方法结合了 DRAM 核心传感过程的分层线性高斯模型和 DRAM 单元泄漏的对数正态分布模型。获得了分析成品率表达式，发现它由两个独立的源主导——单元泄漏分量的对数正态分布或高斯分布，具体取决于阵列结构参数、寄生参数和读出放大器偏移电压。针对几种不同的 DRAM 架构进行了良率分析，并与信号裕度分析和数据保留测试的测量结果进行了比较。发现收益率模型非常准确。由于计算时间短，它可以轻松应用于新型阵列结构的分析和成品率优化、DRAM 单元泄漏分析、读出放大器偏移电压要求和核心电源电压优化。它还为其他存储器电路的良率设计铺平了道路。
In this paper the electric yield of DRAM core circuits is investigated by means of a statistical approach that incorporates a hierarchical linear Gaussian model for the DRAM core sensing process and a lognormal distribution model for the DRAM cell leakage. Analytical yield expressions are obtained and found to be dominated by two independent sources-either the lognormal distribution of the cell leakage components or the Gaussian distribution depending on the array structural parameters, parasitic, and the sense amplifier offset voltage. Analytical yield analysis is conducted for several different DRAM architectures and compared to measurements from signal margin analysis and data retention tests. The yield model is found to be very accurate. Thanks to the short computation time, it can be easily applied to the analysis and yield optimization of novel array structures, DRAM cell leakage analysis, sense amplifier offset voltage requirements, and core supply voltage optimization. It also paves the way for the design for yield of other memory circuits.