Bistable-Triplet STDP circuit without external memory for Integrating with Silicon Neurons
Bistable-Triplet STDP circuit without external memory for Integrating with Silicon Neurons
复制标题
无需外部存储器即可与硅神经元集成的双稳态三重态 STDP 电路
DOI：
10.1109/aiiot52608.2021.9454167
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发表时间：
2021
期刊：
影响因子：
--
通讯作者：
B. Kailath
中科院分区：
文献类型：
--
作者：
S. S;B. Kailath
尖峰神经网络可以适应环境，如果它有能力基于尖峰时间依赖可塑性（STDP）进行学习，通过STDP，突触权重基于突触前和突触后尖峰之间的时间差进行修改。经典的基于对的STDP模型只考虑了一对前和后尖峰，当由一系列尖峰驱动时，该模型未能解释突触活动。然而，基于三重态的STDP模型为实验数据提供了最佳拟合，并映射到Bienenstock-Cooper-Munro（B-S）学习规则。在电路级实现可塑性规则是实现有效的计算超大规模集成电路（VLSI）系统，其中包括学习和记忆功能。到目前为止，文献中的TSTDP的模拟VLSI实现需要外部电路来识别两个直接连续的前和后尖峰之间的精确定时。本文提出的TSTDP电路能够识别任何两个尖峰之间的精确时间差，根据时间差的符号和强度提供增强或抑制，并且在使用泊松尖峰序列驱动时也继承了增强规则。该电路已经在LTspice-XVII中使用“TSMC 180 nm”工艺库进行了仿真。
Spiking Neural Network can adapt to the environment if it has the capacity to learn based on spike timing-dependent plasticity (STDP) by which the synaptic weight gets modified based on time difference between pre and postsynaptic spikes. The classical pair-based STDP model which considers only a pair of pre and post spikes has failed to account for synaptic activity when driven by a series of spikes. Whereas, Triplet based STDP model provides best fit for the experimental data as well as maps on to the Bienenstock-Cooper-Munro (BCM) learning rule. Implementation of plasticity rules at circuit level is necessary for realizing efficient computational very large scale integration (VLSI) systems which incorporates learning and memory functions. The analog VLSI implementation of TSTDP available in literature so far requires external circuitry to identify precise timing between two immediate successive pre and post spikes. The TSTDP circuit proposed in this paper is capable of identifying precise time difference between any two spikes, provides potentiation or depression based on sign and strength of the time difference, and also inherits the BCM rule when driven with Poisson spike trains. The circuit has been simulated in LTspice-XVII with the “TSMC 180nm” technology library.