Characterization of HYPRES' 4.5 kA/cm/sup 2/ & 8 kA/cm/sup 2/ Nb/AlO/sub x//Nb fabrication processes
Characterization of HYPRES' 4.5 kA/cm/sup 2/ & 8 kA/cm/sup 2/ Nb/AlO/sub x//Nb fabrication processes
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HYPRES 4.5 kA/cm/sup 2/ 的表征
DOI：
10.1109/tasc.2005.849701
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发表时间：
2005
影响因子：
1.8
通讯作者：
V. Semenov
中科院分区：
文献类型：
--
作者：
D. Yohannes;S. Sarwana;S. K. Tolpygo;A. Sahu;Y. Polyakov;V. Semenov
HYPRES 开发了更高临界电流密度约瑟夫森结 (JJ) 的新制造工艺。这些工艺结合了用于结绝缘的额外阳极氧化步骤，从而能够制造小至亚微米尺寸的结。采用了一套新的处理工具，包括铌和铝的高密度 (ICP) 等离子体蚀刻，以及来自 TEOS 源的层间电介质 (SiO/sub 2/) 的低温等离子体增强化学气相沉积。设计并实现了一套新型参数控制监视器（PCM）测试芯片。给出了 JJ、布线和接触孔蚀刻的电学和 SEM 表征结果。讨论了临界电流分布和分流电阻均匀性以及结形状的影响。 4.5 kA/cm/sup 2/ 工艺已实现 1.2% 的临界电流 1/spl sigma/ 分布。
HYPRES has developed new fabrication processes for higher critical current density Josephson junctions (JJs). These processes incorporate an additional anodization step for junction insulation, which enables fabrication of junctions down to submicron sizes. A set of new processing tools has been employed, including a high density (ICP) plasma etching of niobium and aluminum, and low temperature plasma-enhanced chemical vapor deposition of interlayer dielectric (SiO/sub 2/) from a TEOS source. A set of new parametric control monitor (PCM) test chips has been designed and implemented. Results of electric and SEM characterization of JJ's, wiring, and contact-hole etching are presented. The critical current spreads and shunt resistance uniformity along with the effects of junction shape are discussed. The critical current 1/spl sigma/ spreads of 1.2% have been achieved for the 4.5 kA/cm/sup 2/ process.