A Personal-Use Single-Chip Emulator Using Dynamically Reconfigurable Logic Array
A Personal-Use Single-Chip Emulator Using Dynamically Reconfigurable Logic Array
复制标题
使用动态可重构逻辑阵列的个人用单片仿真器
DOI：
10.1109/asscc.2005.251732
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
T. Ohmi
中科院分区：
文献类型：
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作者：
K. Kotani;N. Miyamoto;T. Ohkawa;A. Jamak;S. Kita;T. Ohmi
本文介绍了一个使用动态可重构逻辑阵列的个人用单芯片仿真系统FP2。它可以通过对目标电路划分出的子电路的顺序执行来仿真大型目标电路。用于仿真的目标电路的大小在理论上是无限的。为了实现这些功能，FP2配备了时间通信模块（TCM）和灵活的逻辑元件（FLE），这是必要的，以处理划分的子电路之间的时间数据通信和减少配置数据的量，分别。还开发了一个用于FP2的布局布线工具PEOPLE，它负责按顺序执行划分的子电路，并进行时间划分、空间划分、布局、布线和配置数据生成。我们已经开发了一个印刷电路板上的单芯片仿真系统，并证实它的仿真速度比Verilog仿真器快几百倍，在某些情况下也比使用许多并行连接的FPGA的常规仿真器快
A personal-use single-chip emulation system using a dynamically reconfigurable logic array named flexible processor II (FP2) has been developed. It can emulate large target circuit by sequential execution of sub-circuits divided from the target circuit. The size of the target circuit for emulation is theoretically unlimited. In order to realize such features, FP2 is equipped with temporal communication module (TCM) and flexible logic element (FLE), which are essential for handling temporal data communication between divided sub-circuits and for reducing the amount of configuration data, respectively. A place-and-route tool for FP2 named PELOC, which takes care of sequential execution of divided sub-circuits and carries out the temporal partitioning, spatial partitioning, placement, routing and configuration data generation has also been developed. We have developed a single-chip emulation system on a printed circuit board and confirmed that its emulation speed is several hundred times faster than that of Verilog simulator and in some cases also faster than a conventional emulator using lots of parallel-connected FPGAs