Roughness Suppression in Electrochemical Nanoimprinting of Si for Applications in Silicon Photonics
Roughness Suppression in Electrochemical Nanoimprinting of Si for Applications in Silicon Photonics
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硅电化学纳米压印中的粗糙度抑制在硅光子学中的应用
DOI：
10.1002/adma.202206608
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发表时间：
2022
影响因子：
29.4
通讯作者：
Azeredo, Bruno
中科院分区：
文献类型：
--
作者：
Sharstniou, Aliaksandr;Niauzorau, Stanislau;Hardison, Anna L.;Puckett, Matthew;Krueger, Neil;Ryckman, Judson D.;Azeredo, Bruno
金属辅助电化学纳米压印（Mac-Imprint）可扩展硅中微米级和纳米级 3D 自由几何形状的制造，并有望实现在近红外光谱下运行的新型芯片级光学器件。然而，硅的 Mac-Imprint 会同时产生介观粗糙度（例如，突起尺寸约 45 nm），从而产生令人望而却步的光散射水平。这是因为需要在印模上涂上纳米孔金催化剂，在维持蚀刻剂扩散的同时，将其孔（例如，平均直径约 42 nm）压印到硅上。在这项工作中，通过在远离平衡的条件下脱合金来减小催化剂的孔径，粗糙度被降低到亚 10 nm 水平，这与等离子蚀刻相当。在这个水平上，单位数纳米细节（例如催化剂的晶界凹槽）被压印并归因于 Mac-Imprint 的分辨率极限，该极限被认为是德拜长度的两倍（即 1.7 nm）——这一发现广泛适用于金属辅助化学蚀刻。最后，Mac-Imprint 用于在预图案绝缘体硅晶圆上生产单模肋状波导，其均方根线边缘粗糙度小于 10 nm，同时提供深度均匀性（即 42.9 ± 5.5 nm）和有限水平的硅缺陷形成（例如拉曼峰位移 < 0.1 cm−1）和侧壁散射。
Metal‐assisted electrochemical nanoimprinting (Mac‐Imprint) scales the fabrication of micro‐ and nanoscale 3D freeform geometries in silicon and holds the promise to enable novel chip‐scale optics operating at the near‐infrared spectrum. However, Mac‐Imprint of silicon concomitantly generates mesoscale roughness (e.g., protrusion size ≈45 nm) creating prohibitive levels of light scattering. This arises from the requirement to coat stamps with nanoporous gold catalyst that, while sustaining etchant diffusion, imprints its pores (e.g., average diameter ≈42 nm) onto silicon. In this work, roughness is reduced to sub‐10 nm levels, which is in par with plasma etching, by decreasing pore size of the catalyst via dealloying in far‐from equilibrium conditions. At this level, single‐digit nanometric details such as grain‐boundary grooves of the catalyst are imprinted and attributed to the resolution limit of Mac‐Imprint, which is argued to be twice the Debye length (i.e., 1.7 nm)—a finding that broadly applies to metal‐assisted chemical etching. Last, Mac‐Imprint is employed to produce single‐mode rib‐waveguides on pre‐patterned silicon‐on‐insulator wafers with root‐mean‐square line‐edge roughness less than 10 nm while providing depth uniformity (i.e., 42.9 ± 5.5 nm), and limited levels of silicon defect formation (e.g., Raman peak shift < 0.1 cm−1) and sidewall scattering.