Area-efficient synthesis of fault-secure NoC switches
Area-efficient synthesis of fault-secure NoC switches
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DOI：
10.1109/iolts.2014.6873662
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发表时间：
2014-07
期刊：
影响因子：
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通讯作者：
Atefe Dalirsani;M. Kochte;H. Wunderlich
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文献类型：
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作者：
Atefe Dalirsani;M. Kochte;H. Wunderlich
本文介绍了一种混合方法来合成面积高效的故障安全 NoC 交换机，以检测交换机和互连链路中任何单点组合或转换故障所导致的所有错误。首先，识别始终可通过片级数据编码检测到的结构故障。接下来，以最小化面积构建故障安全结构，以便在任何给定输入向量下检测到由剩余故障引起的错误。实验评估表明，与传统的故障安全方案相比，可以显着节省面积。此外，生成的结构可以重复用于测试压实。这减少了测试响应数据量和测试时间，而不会损失故障覆盖率或诊断分辨率。
This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect links. Firstly, the structural faults that are always detectable by data encoding at flit-level are identified. Next, the fault-secure structure is constructed with minimized area such that errors caused by the remaining faults are detected under any given input vector. The experimental evaluation shows significant area savings compared to conventional fault-secure schemes. In addition, the resulting structure can be reused for test compaction. This reduces the amount of test response data and test time without loss of fault coverage or diagnostic resolution.