Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis
Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis
复制标题
DOI：
10.1109/date.2010.5456940
复制
发表时间：
2010-03
期刊：
影响因子：
--
通讯作者：
Masood Qazi;M. Tikekar;L. Dolecek;Devavrat Shah;A. Chandrakasan
中科院分区：
文献类型：
--
作者：
Masood Qazi;M. Tikekar;L. Dolecek;Devavrat Shah;A. Chandrakasan
深亚微米技术中工艺变化的影响对于SRAM架构尤其明显，SRAM架构必须在增加的集成度下满足更高密度和更高性能的需求。由于SRAM的结构复杂，准确估计工艺变化的影响变得非常具有挑战性。在本文中，我们解决这一挑战的背景下，估计SRAM的时序变化。具体来说，我们介绍了一种方法，称为循环平坦化，演示了如何评估的时序统计在复杂的，高度结构化的电路可以减少到一个单一的组件电路链。然后非常快速地评估一个单一的链的时间延迟，我们采用了一种统计方法的基础上的重要性抽样增强有针对性的，高维，球形采样。总的来说，我们的方法提供了一个准确的估计与650倍或更大的速度超过标称蒙特卡罗方法。
The impact of process variation in deep-submicron technologies is especially pronounced for SRAM architectures which must meet demands for higher density and higher performance at increased levels of integration. Due to the complex structure of SRAM, estimating the effect of process variation accurately has become very challenging. In this paper, we address this challenge in the context of estimating SRAM timing variation. Specifically, we introduce a method called loop flattening that demonstrates how the evaluation of the timing statistics in the complex, highly structured circuit can be reduced to that of a single chain of component circuits. To then very quickly evaluate the timing delay of a single chain, we employ a statistical method based on importance sampling augmented with targeted, high-dimensional, spherical sampling. Overall, our methodology provides an accurate estimation with 650X or greater speed-up over the nominal Monte Carlo approach.