Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal-Oxide-Semiconductor Transistors Using High-k Dielectric
Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal-Oxide-Semiconductor Transistors Using High-k Dielectric
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DOI：
10.1109/led.2015.2393913
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发表时间：
2015-03-01
影响因子：
4.9
通讯作者：
Zhang, Changchun
中科院分区：
文献类型：
--
作者：
Guo, Yufeng;Yao, Jiafei;Zhang, Changchun
通过线性增加漂移区宽度和高k介电区，提出了一种新的横向宽度变化(VLW)技术，以均匀等电势轮廓和增加漂移掺杂浓度，从而最大限度地提高击穿电压和降低比导通电阻。VLW横向双扩散金属氧化物半导体(LDMOS)的击穿电压超过600V，绝缘层厚度为1微米，埋氧层厚度为3微米，漂移区长度为60微米。三维模拟表明，与相同几何参数的常规(Conv)器件相比，该器件的击穿电压提高了140%，而导通电阻降低了50%。此外，VLW LDMOS的品质因数最高，分别是常规器件、横向掺杂变化和横向厚度变化的优值系数的10倍、1.8倍和4.5倍。
By employing the linear increasing drift region width and the high-k dielectric region, a novel variation of lateral width (VLW) technique is proposed to even the equipotential contour and increase the drift doping concentration, which maximize the breakdown voltage and reduce the specific ON-resistance. The breakdown voltage exceeds 600 V on the VLW lateral double-diffused metal-oxide-semiconductor (LDMOS) with 1-mu m silicon-on-insulator layer, 3-mu m buried oxide, and 60-mu m drift region length. The 3-D simulation indicates that the proposed device increases the breakdown voltage by 140%, while reduces the specific ON-resistance by 50% in comparison with the conventional (CONV) device with the same geometric parameters. Moreover, VLW LDMOS presents the best figure of merit, which is 10, 1.8, and 4.5 times higher than that of CONV, variation of lateral doping, and variation of lateral thickness devices, respectively.