Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
复制标题
基于统计估计的硅后时钟时序调整
DOI：
10.1093/ietfec/e91-a.9.2322
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
Yuichi Nakamura
中科院分区：
文献类型：
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作者：
Y. Hashizume;Y. Takashima;Yuichi Nakamura
在深亚微米技术中，工艺变化会显着影响 VLSI 芯片的性能和产量。作为针对这些变化的对策，已经提出了硅后调谐。相差校正方法属于这种方法，其中通过在时钟树中插入可编程延迟元件 (PDE) 来调整触发器 (FF) 的时钟时序。我们提出了一种新颖的相差校正方法，该方法通过测量少量 FF 的时钟时序并基于统计模型推测其余 FF 的时钟时序来确定元件的延迟值。此外，我们提出的方法可以确定离散 PDE 延迟值，因为重写约束满足总单模性条件。
In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.