A digital architecture employing stochasticism for the simulation of Hopfield neural nets
A digital architecture employing stochasticism for the simulation of Hopfield neural nets
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采用随机性模拟 Hopfield 神经网络的数字架构
DOI：
10.1109/31.31321
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发表时间：
1989
期刊：
影响因子：
--
通讯作者：
T. Miller
中科院分区：
文献类型：
--
作者：
D. V. D. Bout;T. Miller
描述了一种使用随机逻辑来模拟 Hopfield 神经网络行为的数字架构。这种随机架构提供了大规模并行性（因为随机逻辑非常节省空间）、可重编程性（因为突触权重存储在数字移位寄存器中）、大动态范围（通过使用定点或浮点权重）、退火（通过将可变神经元增益与随机算术噪声耦合）、高执行速度（大约=N*10/sup 8/每秒连接数）、可扩展性（通过级联多个芯片来托管大型处理器）。网络）和实用性（通过使用非常保守的 MOS 器件技术构建）。给出的模拟结果表明随机架构给出的结果与使用标准模拟神经网络或模拟退火得到的结果类似。 >
A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides massive parallelism (since stochastic logic is very space-efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynamic range (by using either fixed- or floating-point weights), annealing (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speed ( approximately=N*10/sup 8/ connections per second), expandability (by cascading of multiple chips to host large networks), and practicality (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing. >