Measuring the Performance and Intrinsic Variability of Evolved Circuits
Measuring the Performance and Intrinsic Variability of Evolved Circuits
复制标题
DOI：
10.1007/978-3-642-15323-5_1
复制
发表时间：
2010-09
期刊：
影响因子：
--
通讯作者：
James Alfred Walker;J. Hilder;A. Tyrrell
中科院分区：
文献类型：
--
作者：
James Alfred Walker;J. Hilder;A. Tyrrell
本文提出了一个2位加法器和2位乘法器的传统和多目标笛卡尔遗传规划进化设计之间的比较。每个设计都通过使用开源标准单元库从门级原理图转换为晶体管级实现，并在NGSPICE中进行仿真，以生成行业标准指标，如传播延迟和动态功耗。此外，进行统计固有变异性分析，以了解在尖端技术节点制造时，每个设计如何受到固有变异性的影响。结果表明，2位加法器的进化设计比传统设计更慢，消耗更多的功率。2位乘法器的进化设计被发现比传统设计更快，但消耗更多的功率，并且它对时序和功率的固有变化的影响也更宽容。这提供了证据表明，在未来，基于进化的方法可能是一种可行的替代方案，用于优化尖端技术节点的设计，传统的设计方法不再适用，提供有关标准单元库的速度和功率信息。
This paper presents a comparison between conventional and multi-objective Cartesian Genetic Programming evolved designs for a 2-bit adder and a 2-bit multiplier. Each design is converted from a gate-level schematic to a transistor level implementation, through the use of an open-source standard cell library, and simulated in NGSPICE in order to generate industry standard metrics, such as propagation delay and dynamic power. Additionally, a statistical intrinsic variability analysis is performed, in order to see how each design is affected by intrinsic variability when fabricated at a cutting-edge technology node. The results show that the evolved design for the 2-bit adder is slower and consumes more power than the conventional design. The evolved design for the 2-bit multiplier was found to be faster but consumed more power than the conventional design, and that it was also more tolerant to the effects of intrinsic variability in both timing and power. This provides evidence that in the future, evolutionary-based approaches could be a feasible alternative for optimising designs at cutting-edge technology nodes, where traditional design methodologies are no longer appropriate, providing speed and power information about the standard cell library is used.