Fast and Area-Efficient SRAM Word-Line Optimization
Fast and Area-Efficient SRAM Word-Line Optimization
复制标题
快速且节省空间的 SRAM 字线优化
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Matthew R. Guthaus
中科院分区：
文献类型：
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作者：
Bin Wu;J. Stine;Matthew R. Guthaus
字线驱动器控制静态随机存取存储器（SRAM）中的行中的单元的存取，并且对SRAM速度和功耗具有显著影响。当门延迟是主要因素时，简单的模型是快速字线的良好指导。然而，当行尺寸较大时，布线线延迟是显著的，这导致这些设计是次优的。本文提出了一种分析优化技术，使用延迟模型，包括门延迟，线电阻，线电容，以优化高性能字线驱动器的SRAM的拓扑结构。所提出的方法具有最大45%的延迟改善和42%的缓冲器成本降低。
A word line driver controls the access of cells in a row in Static Random Access Memories (SRAMs) and has a significant impact on SRAM speed and power consumption. When gate delay is the dominant factor, simple models are a good guideline for fast word lines. However, routing wire delay is significant when the row size is large, which causes these designs to be suboptimal. This paper presents an analytical optimization technique using a delay model that includes gate delay, wire resistance, and wire capacitance to optimize high-performance word line driver topologies for SRAMs. The proposed methodology has a maximum 45% delay improvement and 42% buffer cost reduction.