Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
复制标题
昏昏欲睡的指令缓存。
DOI：
10.1109/micro.2002.1176252
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
T. Mudge
中科院分区：
文献类型：
--
作者：
N. Kim;K. Flautner;D. Blaauw;T. Mudge
片上缓存占微处理器总功耗的相当大一部分。虽然大型缓存可以显著提高性能，但它们有可能增加功耗。随着特征尺寸的缩小，这种功率损耗的主要组成部分将是泄漏。在我们之前的工作中，我们已经展示了如何使用昏昏欲睡的电路-一个简单的，状态保持，低泄漏电路，依赖于电压缩放泄漏减少-可以用来减少数据缓存的总能耗超过50%。在本文中，我们扩展的架构控制机制的昏昏欲睡的高速缓存，以减少泄漏功耗的指令高速缓存的执行时间没有显着的影响。我们的研究结果表明，数据和指令高速缓存需要不同的控制策略，有效的执行。为了使指令高速缓存，我们提出了一种技术，称为高速缓存子库预测，这是用来选择性地唤醒只有必要的部分的指令高速缓存，同时允许大部分的该高速缓存，以保持在一个低泄漏困倦模式。与无预测策略相比，这种预测技术将负面性能影响降低了76%。我们的技术工作得很好，即使与小预测器的大小，并使泄漏能量减少86%，在64 K字节的指令缓存。
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. In our previous work we have shown how the drowsy circuit - a simple, state-preserving, low-leakage circuit that relies on voltage scaling for leakage reduction - can be used to reduce the total energy consumption of data caches by more than 50%. In this paper, we extend the architectural control mechanism of the drowsy cache to reduce leakage power consumption of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. To enable drowsy instruction caches, we propose a technique called cache sub-bank prediction which is used to selectively wake up only the necessary parts of the instruction cache, while allowing most of the cache to stay in a low leakage drowsy mode. This prediction technique reduces the negative performance impact by 76% compared to the no-prediction policy. Our technique works well even with small predictor sizes and enables an 86% reduction of leakage energy in a 64 K byte instruction cache.