Aging-based leakage energy reduction in FPGAs
Aging-based leakage energy reduction in FPGAs
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DOI：
10.1109/fpl.2013.6645562
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发表时间：
2013-10
期刊：
影响因子：
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通讯作者：
Sheng Wei;J. Zheng;M. Potkonjak
中科院分区：
文献类型：
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作者：
Sheng Wei;J. Zheng;M. Potkonjak
深亚微米工艺中工艺变异(PV)的存在已成为对现场可编程门阵列(FGA)进行能量优化尝试的主要问题。我们开发了一种基于负偏压温度不稳定性(NBTI)老化的硅后漏能量优化方案，该方案重点关注未使用或偏离关键路径的元件，以降低总的漏能量消耗。此外，我们通过将老化目标描述为可满足性(SAT)问题来获得老化的输入向量。我们综合了Xilinx Spartan6现场可编程门阵列的低功耗设计，并在一组ITC99和Opencores基准测试上评估了漏电节能效果。
The presence of process variation (PV) in deep submicron technologies has become a major concern for energy optimization attempts on FPGAs. We develop a negative bias temperature instability (NBTI) aging-based post-silicon leakage energy optimization scheme that stresses the components that are not used or are off the critical paths to reduce the total leakage energy consumption. Furthermore, we obtain the input vectors for aging by formulating the aging objectives into a satisfiability (SAT) problem. We synthesize the low energy design on Xilinx Spartan6 FPGA and evaluate the leakage energy savings on a set of ITC99 and Opencores benchmarks.