Fully-functional FPGA prototype with fine-grain programmable body biasing
Fully-functional FPGA prototype with fine-grain programmable body biasing
复制标题
具有细粒度可编程体偏置的全功能 FPGA 原型
DOI：
10.1145/2435264.2435280
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
T. Tsutsumi
中科院分区：
文献类型：
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作者：
M. Hioki;T. Sekigawa;T. Nakagawa;H. Koike;Y. Matsumoto;Takashi Kawanami;T. Tsutsumi
采用低功耗90纳米体CMOS技术制作了一个全功能的FPGA原型芯片，其中可编程体偏置电压可以单独应用于mux， LUT和DFF等元素电路，并在硅上评估了面积开销，动态电流，静态电流和运行速度。在测量中，采用新开发的CAD工具实现了10个ISCAS基准电路，这些工具包括VT映射器、砂矿机和路由器。掩模布局显示，分隔良好的边距、可编程体偏置电路和额外的配置存储器占据了54%的FPGA面积。测试结果表明，该FPGA可使静态电流平均降低91.4%。此外，通过实现具有不同体偏置电压对的环形振荡器的评估表明，通过分别在关键路径上为mosfet分配低阈值电压和高阈值电压，静态电流从23.1 uA降低到1.0 uA，同时保持与所有mosfet分配低阈值电压时相同的6.6 MHz振荡频率。此外，细粒度可编程体偏置技术通过积极施加正向体偏置电压来加速FPGA上实现的环形振荡器的振荡频率，而通过施加反向体偏置在非关键路径上为mosfet分配HVT有效地抑制了正向体偏置引起的静态电流指数增长。
A fully-functional FPGA prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the FPGA tile area. Measurement results show that the fabricated FPGA reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on FPGA by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing.