A fine resolution TDC architecture for next generation PET imaging
A fine resolution TDC architecture for next generation PET imaging
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DOI：
10.1109/tns.2007.903183
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发表时间：
2007-10-01
影响因子：
1.8
通讯作者：
Haslett, James W.
中科院分区：
文献类型：
--
作者：
Yousif, Abdel S.;Haslett, James W.
提出了一种高分辨率和工艺可扩展的 CMOS 时间数字转换器 (TDC) 架构。使用新架构的 6 位高分辨率 TDC 设计针对正电子发射断层扫描 (PET) 成像应用进行了评估。 TDC架构采用分层延迟处理结构来实现单周期延迟和高速运行。该精细分辨率转换器采用 130 nm CMOS 实现，设计为在 500 MHz 的参考时钟频率下运行，但可以通过时间交织扩展到多 GHz 运行。无需外部校准，TDC 即可用作具有 4.65 ENOB（有效位数）的 5 位精细分辨率转换器。在此条件下，6 位 TDC 的 INL（积分非线性）测量值小于 1.45 LSB，DNL（微分非线性）测量值小于 1.25 LSB。通过外部校准，INL/DNL 非线性度降低了 50% 以上，将 ENOB 提高到 5.5 位，从而将 TDC 推向 6 位精细分辨率操作。 TDC 的定时分辨率为 31 ps，功耗低于 1 mW。该设计被认为是文献中速度最快、功耗最低的精细分辨率 TDC。
A fine resolution and process scalable CMOS time-to-digital converter (TDC) architecture is presented. A 6-bit fine resolution TDC design using the new architecture is evaluated for positron emission tomography (PET) imaging application. The TDC architecture uses a hierarchical delay processing structure to achieve single cycle latency and high speed of operation. The fine resolution converter, realized in 130 nm CMOS, is designed to operate over a reference clock frequency of 500 MHz but can be scaled to multi GHz operation through time interleaving. Without external calibration, the TDC is used as a 5-bit fine resolution converter with 4.65 ENOB (Effective Number Of Bits). Under this condition, the 6-bit TDC has an INL (Integral Non-Linearity) measurement of less than 1.45 LSB and a DNL (Differential Non-Linearity) measurement of less than 1.25 LSB. With external calibration, a reduction of more than 50% in INL/DNL nonlinearities is demonstrated improving the ENOB to 5.5 bits, pushing the TDC to a 6-bit fine resolution operation. The TDC has a 31 ps timing resolution and power consumption of less than 1 mW. The design is believed to be the fastest and the lowest power consuming fine resolution TDC in the literature.