Analysis of Random Telegraph Noise in 45-nm CMOS Using On-Chip Characterization System
Analysis of Random Telegraph Noise in 45-nm CMOS Using On-Chip Characterization System
复制标题
使用片上表征系统分析 45 nm CMOS 中的随机电报噪声
DOI:
10.1109/ted.2013.2254118
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发表时间:
2013
影响因子:
3.1
通讯作者:
K. Shepard
中科院分区:
文献类型:
--
作者:
S. Realov;K. Shepard
An on-chip variability characterization system implemented in a 45-nm CMOS process is used for direct time-domain measurements of random telegraph noise (RTN) in small-area devices. A procedure for automated extraction of RTN parameters from large volumes of measured data is developed. Statistics for number of traps, NT, and single-trap amplitudes, ΔV<sub>th</sub>, are studied across device polarity, bias, and gate area. A Poisson distribution is used to model NT and a log-normal distribution is used to model ΔV<sub>th</sub>. The scaling of the two statistics across gate dimensions is discussed; the expected value of NT is shown to scale with (L - ΔL)<sup>-1</sup>, whereas the expected value of AV<sub>th</sub> is shown to scale with W<sup>-1</sup>(L - ΔL)<sup>-0.5</sup>. The two statistics are combined in a compact RTN probabilistic model representing the statistics of the overall ΔV<sub>th</sub> fluctuations because of RTN. This model is demonstrated to give accurate predictions of the tails of the measured RTN distributions at the 95th percentile level, which scale with W<sup>-1</sup>(L - ΔL)<sup>-1.5</sup>. A comparison between nMOS and pMOS devices shows that pMOS devices exhibit both a higher average number of traps and a larger average single-trap ΔV<sub>th</sub> amplitude, leading to a comparatively larger overall impact of RTN.