A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS
A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS
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采用 65 nm LL-HVT CMOS 的 < 1 pJ 亚 VT 心脏事件检测器
DOI：
10.1109/vlsisoc.2010.5642669
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
V. Öwall
中科院分区：
文献类型：
--
作者：
J. Rodrigues;Omer Can Akgun;V. Öwall
本文介绍了用于心脏起搏器的基于小波的事件检测器的硬件实现。应用高水平能量估计流程来评估基于标准单元的设计的能量效率，这些设计在几代 CMOS 技术（从 180 到 65 nm）中运行，在亚阈值域中运行。仿真结果表明 65 nm 低泄漏高阈值 (LL-HVT) CMOS 技术是最佳选择。因此，该设计采用 65nm LL-HVT CMOS 制造。测量验证了仿真结果，并证明电路在电源电压低至 250mV 时仍能正常工作。在能量最小电压为 320mV 时，电路在时钟速率为 20 kHz 时每个样本消耗 0.88 pJ。
This paper presents the hardware implementation of a wavelet based event detector for cardiac pacemakers. A high level energy estimation flow was applied to evaluate energy efficiency of standard-cell based designs, over several CMOS technology generations, from 180 to 65 nm, operated in the sub-threshold domain. The simulation results indicate a 65 nm low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250mV. At the energy minimum voltage of 320mV the circuit dissipates 0.88 pJ per sample at a clock rate of 20 kHz.