Strain relaxation in semiconductor wafer bonding
Strain relaxation in semiconductor wafer bonding
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DOI：
10.35848/1347-4065/abf9e4
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发表时间：
2021-05
影响因子：
1.5
通讯作者：
K. Tanabe
中科院分区：
文献类型：
--
作者：
K. Tanabe
与外延生长形成的半导体异质结构不同，本文对晶圆键合半导体异质结构中的应变弛豫过程进行了数值研究。针对高度晶格失配的异质结构，重新建立了半导体层中应变弛豫的动力学模型。然后利用该模型进行数值模拟，以分析应变、应变速率和失配位错密度随时间的演化。计算结果表明，在比外延生长温度更低的情况下进行晶圆键合的晶格失配异质结构中，呈现出缓慢的应变弛豫行为，通过使材料系统保持在亚稳态来抑制热力学上更易产生的位错。对于晶格失配度为0.04的情况，在晶圆键合温度（以熔点温度归一化）处于0.2 - 0.4的典型范围内，应变弛豫的时间常数为3×10⁵ - 2×10²¹秒。这种弛豫时间与在典型归一化温度为0.6的异质外延情况下的14秒形成对比，从而证明了晶圆键合中的非平衡晶体稳定性。
The strain relaxation process in wafer-bonded semiconductor heterostructures is numerically investigated, in contrast to those formed by epitaxial growth. A kinetic model of strain relaxation in semiconductor layers is re-established for highly lattice-mismatched heterostructures. Numerical simulations are then performed by using the model to analyze the time evolution of the strain, the strain rate, and the misfit dislocation density. The calculation results present a slow strain relaxation behavior in the lattice-mismatched heterostructures wafer-bonded at lower temperatures than those for epitaxial growth, to suppress the thermodynamically preferred dislocation generation by sustaining the material system at a metastable state. The time constant of strain relaxation in a typical range of wafer bonding temperatures, normalized by the melting temperature, of 0.2–0.4 is found to be 3 × 105–2 × 1021 s for a lattice mismatch of 0.04. This relaxation time contrasts with 14 s for the case of heteroepitaxy at a typical normalized temperature of 0.6, thus evidencing the nonequilibrium crystalline stability in wafer bonding.