Worst-case delay analysis considering the variability of transistors and interconnects
Worst-case delay analysis considering the variability of transistors and interconnects
复制标题
考虑晶体管和互连的可变性的最坏情况延迟分析
DOI：
10.1145/1231996.1232006
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
H. Onodera
中科院分区：
文献类型：
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作者：
Takayuki Fukuoka;A. Tsuchiya;H. Onodera
本文讨论了在互连结构和晶体管性能波动的情况下，给出一级统计最坏时延的条件。一个级的延迟是许多参数的函数，如栅极的驱动强度、互连长度和互连结构（宽度、厚度、间距等），因此最坏情况下的延迟条件也成为这些参数的函数。我们使用一个简单的等效电路来检查最坏情况，并显示最坏情况是如何变化的。结果表明，在一定的互连长度范围内，互连结构的最坏情况向其他互连长度范围内的最佳情况移动，因此正确定位最坏情况对于准确估计最坏阶段延迟具有重要意义。我们给出了互连结构最坏情况方向的一个简单准则。
This paper discusses the condition that gives the statistical worst-casedelay of a stage under the fluctuation of interconnect structure and transistor performance. The delay of a stage is a function of many parameters such as drive strength of the gate, interconnect length and interconnect structures (width, thickness, spacing, etc.), and therefore the condition for the worst-case delay also becomes a function of those parameters. We examine the worst-case condition using a simple equivalent circuit and show how the worst-case condition varies. It is shown that the worst-case condition of an interconnect structure for a certain range of interconnect length moves toward the best-case for other range of interconnect length, and hence it is important to locate the worst-case condition correctly for accurate estimation of the worst-case stage delay. We show a simple criteria for the direction of the worst-case condition of an interconnect structure.