Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection
复制标题
重用验证断言作为硬件木马检测的安全检查器
DOI：
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发表时间：
2022
期刊：
影响因子：
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通讯作者：
S. Pagliarini
中科院分区：
文献类型：
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作者：
Mohammad Eslami;Tara Ghasempouri;S. Pagliarini
半导体行业的全球化使无晶圆厂设计公司能够降低成本、节省时间并利用更新的技术。然而，集成电路（IC）制造的离岸外包也有消极的一面，包括硬件木马（ht）等威胁，这是一种很难检测到的恶意逻辑。IC设计不受全球化影响的一个方面是需要彻底的验证。验证工程师设计复杂的资产以确保设计没有错误，包括断言。一旦验证结束，这些知识通常不会被重用。本文的前提是可以将已经存在的验证资产转化为有效的HT检测安全检查器。为此，我们将展示如何将断言用作在线监视器。为此，我们提出了利用Cadence JasperGold安全路径验证（SPV）的安全度量和断言选择流。实验结果表明，通过分析100多个OpenTitan片上系统（SoC）不同知识产权（ip）的断言，我们的方法适用于工业规模的电路。此外，我们的检测方案是实用的，因为它不依赖于HT激活机制。
Globalization in the semiconductor industry enables fabless design houses to reduce their costs, save time, and make use of newer technologies. However, the offshoring of Integrated Circuit (IC) fabrication has negative sides, including threats such as Hardware Trojans (HTs) – a type of malicious logic that is not trivial to detect. One aspect of IC design that is not affected by globalization is the need for thorough verification. Verification engineers devise complex assets to make sure designs are bug-free, including assertions. This knowledge is typically not reused once verification is over. The premise of this paper is that verification assets that already exist can be turned into effective security checkers for HT detection. For this purpose, we show how assertions can be used as online monitors. To this end, we propose a security metric and an assertion selection flow that leverages Cadence JasperGold Security Path Verification (SPV). The experimental results show that our approach scales for industry-size circuits by analyzing more than 100 assertions for different Intellectual Properties (IPs) of the OpenTitan System-on-Chip (SoC). Moreover, our detection solution is pragmatic since it does not rely on the HT activation mechanism.