Using Hard Macros to Reduce FPGA Compilation Time
Using Hard Macros to Reduce FPGA Compilation Time
复制标题
使用硬宏减少 FPGA 编译时间
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
M. Wirthlin
中科院分区：
文献类型：
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作者：
C. Lavin;M. Padilla;Subhrashankha Ghosh;B. Nelson;B. Hutchings;M. Wirthlin
FPGA汇编过程（合成，地图，放置，路由）是一个耗时的过程，可限制设计人员的生产力。通过使用预编译的电路块（硬宏）可以减少编译时间。硬宏由先前合成的，映射，放置和路由电路组成，这些电路可以相对放置在短的工具运行时，这使得可以重复使用以前的计算工作。进行了两项实验，以证明可行性可以减少编译时间。这些实验表明，专门为支持硬宏而设计的增强Xilinx流可以将整体汇编时间减少3倍。尽管当前将硬宏纳入设计的过程是手动和容易出错的过程，但可以自动化以较低的汇编时间创建编译流。
The FPGA compilation process (synthesis, map, placement, routing) is a time-consuming process that limits designer productivity. Compilation time can be reduced by using pre-compiled circuit blocks (hard macros). Hard macros consist of previously synthesized, mapped, placed and routed circuitry that can be relatively placed with short tool runtimes and that make it possible to reuse previous computational effort. Two experiments were performed to demonstrate feasibility that hard macros can reduce compilation time. These experiments demonstrated that an augmented Xilinx flow designed specifically to support hard macros can reduce overall compilation time by 3x. Though the process of incorporating hard macros in designs is currently manual and error-prone, it can be automated to create compilation flows with much lower compilation time.