Scanning probe nanolithography using self-assembled monolayer for fabrication of single electron transistors
Scanning probe nanolithography using self-assembled monolayer for fabrication of single electron transistors
复制标题
使用自组装单层扫描探针纳米光刻技术制造单电子晶体管
DOI：
10.1109/sensor.2003.1215298
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
H. Fujita
中科院分区：
文献类型：
--
作者：
Y. Isono;K. Shimamoto;G. Hashiguchi;Y. Mihara;H. Mimura;T. Hiramoto;H. Fujita
本研究提出了一种新颖的硅纳米线的制造方法，在隧道结之间的纳米岛单电子晶体管（SET）。采用场增强阳极氧化技术，在硅片表面沉积十八烷基硅烷（ODS）单层膜，进行了基于扫描探针显微镜（SPM）的纳米光刻（SPNL）。以有机硅烷分子组成的ODS单层膜作为抗蚀剂掩模，采用压边力对纳米厚二氧化硅薄膜进行湿法刻蚀。ODS单层纳米图案化，归因于有机硅烷分子的降解，通过扫描与ODS表面和探针之间的偏置电压的导电探针。使用的SPNL与ODS单层，我们已经成功地制造了设置包括纳米硅线与隧道结之间的量子岛。采用快速热氧化法和固相纳米线剥离法在具有ODS单层外涂层的绝缘体上硅晶片上制备了宽40 nm、厚80 nm的硅纳米线。具有40 nm正方形的硅岛也位于导线中心的两个隧道结之间。在用于栅极氧化物的纳米线上生长20 nm厚的SiO/sub 2/之后，隧道结宽度减小。本文还研究了SETs的电学特性。
This research proposes a novel fabrication of silicon nanowire with a nanometric island between tunnel junctions for single electron transistor (SET). The scanning probe microscope (SPM)-based nanolithography (SPNL) using a field-enhanced anodization technique was performed at a surface of octadecylsilyl (ODS) monolayer deposited on a silicon wafer. The ODS monolayer composed of organosilane molecules was used as a resist mask for wet etching of nano-thick silicon dioxide film with BHF. The ODS monolayer was patterned nanometrically, attributed to the degradation of the organosilane molecules by scanning a conductive probe with a bias voltage between the ODS surface and probe. Using the SPNL with the ODS monolayer, we have succeeded in fabricating SETs comprising a nanometric Si wire with a quantum island between tunnel junctions. The silicon nanowire, with a width of 40 nm and a thickness of 80 nm, was entirely accomplished by rapid thermal oxidation and SPNL on a silicon-on-insulator wafer with an overcoat of ODS monolayer. A silicon island with 40 nm-squares was also located between two tunnel junctions at the center of the wire. After growing a 20 nm-thick SiO/sub 2/ on the nanowire for the gate oxide, the tunnel junction width was reduced. The electrical characteristic of the SETs was also examined in this paper.