A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor-猫眼课题宝

DOI：

10.1109/jssc.1996.542315

发表时间：

1996-02

期刊：

IEEE J. Solid State Circuits

影响因子：

通讯作者：

中科院分区：

其他

文献类型：

作者：

J. Montanaro;R. Witek;K. Anne;A. J. Black;E. Cooper;D. Dobberpuhl;P. Donahue;J. Eno;G. Hoeppner;D. Kruckemyer;T. Lee;P. Lin;L. Madden;D. Murray;M. Pearce;S. Santhanam;K. Snyder;R. Stephany;S. Thierauf

本文介绍了一种专为低功耗、低成本应用而设计的160 MHz 500 mW 32 b StrongARM(R)微处理器。该芯片实现了ARM(R) V4指令集，并与早期的实现总线兼容。引脚接口工作在3.3 V，但内部电源可以在1.5到2.2 V之间变化，提供多种选择来平衡性能和功耗。在160 MHz的内部时钟速度和1.65 V的标称Vdd下，它提供185 Dhrystone 2.1 MIPS，而功耗低于450 mW。工作点范围从1.65 V时的100mhz耗散小于300mw到2.0 V时的200mhz耗散小于900mw。片上锁相环提供基于3.68 MHz时钟输入的内部时钟。该芯片包含250万个晶体管，其中90%位于两个16kb的缓存中。它采用0.35-/spl mu/m三金属CMOS工艺制造，阈值为0.35 V，有效通道长度为0.25 /spl mu/m。该芯片尺寸为7.8 mm/spl × /6.4 mm，采用144针塑料薄四平面封装（TQFP）封装。

This paper describes a 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications. The chip implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-/spl mu/m three-metal CMOS process with 0.35 V thresholds and 0.25 /spl mu/m effective channel lengths. The chip measures 7.8 mm/spl times/6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package.

A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor

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