Optimization of Common Source Inductance and Gate-Drain Capacitance for Reducing Gate Voltage Fluctuation after Turn-off Transition

Optimization of Common Source Inductance and Gate-Drain Capacitance for Reducing Gate Voltage Fluctuation after Turn-off Transition
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DOI:
10.1109/ecce44975.2020.9236428
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发表时间:
2020-10
期刊:
2020 IEEE Energy Conversion Congress and Exposition (ECCE)
影响因子:
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通讯作者:
Yusuke Hatakenaka;K. Umetani;Masataka Ishihara;E. Hiraki
Yusuke Hatakenaka;K. Umetani;Masataka Ishihara;E. Hiraki
中科院分区:
其他
文献类型:
--
作者:
Yusuke Hatakenaka;K. Umetani;Masataka Ishihara;E. Hiraki

文献摘要

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作为GaN-FET的下一代开关器件最近成为能够极高速开关的有前途的开关器件。高速开关使功率转换器能够高频工作,从而减小无源元件的尺寸。然而,高速开关会引起开关器件的寄生电容和电路板布线的寄生电感之间的谐振,这表现为开关时的栅极电压波动。特别地,GaN-FET倾向于具有相对低的栅极阈值电压,因此容易受到错误导通的影响,该错误导通是由刚好在关断转变之后的开关器件中的栅极电压波动引起的。为了防止这种现象,本文分析了这些寄生参数的设计要求,以减少关断过渡后的栅极电压波动。结果表明,栅漏电容与共源电感的最佳比值是减小栅压波动的关键。仿真和实验结果表明,该比例的优化设计可以降低栅极电压波动,支持这种新的见解,防止假导通的有用性。
Next-generation switching devices as GaN-FETs are recently emerging as promising switching devices capable of extremely high-speed switching. High-speed switching enables the high-frequency operation of the power converters, which can reduce the size of the passive components. However, high-speed switching can induce the resonance between the parasitic capacitance of the switching device and the parasitic inductance of the circuit board wiring, which appears as the gate voltage fluctuation at the switching. Particularly, GaN-FETs tend to have comparatively low gate threshold voltage and therefore are susceptible to the false turn-on, which is caused by the gate voltage fluctuation in the switching device just after the turn-off transition. For preventing this phenomenon, this paper analytically investigates the design requirement of these parasitic parameters to reduce the gate voltage fluctuation after the turn-off transition. As a result, the optimal ratio of the gate-drain capacitance and the common source inductance is elucidated to be the key to minimize the gate voltage fluctuation. The simulation and the experiment supported that the optimal design of this ratio can reduce the gate voltage fluctuation, supporting the usefulness of this novel insight for preventing the false turn-on.