Transmission Line Pulsing Tester For On-chip ESD Protection Testing

Transmission Line Pulsing Tester For On-chip ESD Protection Testing
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DOI：
10.1109/mixdes.2006.1706650
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发表时间：
2006-06
期刊：
Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.
影响因子：
--
通讯作者：
Z. Piatek;W. Pleskacz;J. Kolodziejski
Z. Piatek;W. Pleskacz;J. Kolodziejski
中科院分区：
其他
文献类型：
--
作者：
Z. Piatek;W. Pleskacz;J. Kolodziejski

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本文介绍了传输线脉冲调制（TLP）方法和测试仪。与通常缺乏测试器设计信息的现有出版物相比，作者描述了TLP测试器的构造细节。这包括一个应用电路图。根据最新的研究和初步的测试结果与组装的张力腿平台试验机的帮助下，提供的结论
In the paper transmission line pulsing (TLP) methodology and testers are described. In contrast to commonly available publications, which usually lack information on testers' design, the authors describe TLP tester's construction details. This includes an applied electric diagram. Conclusions based on up-to-date research and preliminary test results obtained with the help of the assembled TLP tester are provided