IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
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IntAct：96 核处理器，具有 6 个小芯片 3D 堆叠在有源中介层上，具有分布式互连和集成电源管理
DOI：
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发表时间：
2021
影响因子：
5.4
通讯作者：
F. Clermidy
中科院分区：
文献类型：
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作者：
P. Vivet;Eric Guthmuller;Y. Thonnart;G. Pillonnet;César Fuguet;I. Miro;G. Moritz;J. Durupt;C. Bernard;D. Varreau;Julian J. H. Pontes;S. Thuries;David Coriat;M. Harrand;D. Dutoit;D. Lattard;L. Arnaud;J. Charbonnier;P. Coudrain;A. Garnier;F. Berger;A. Gueugnot;A. Greiner;Quentin L. Meunier;A. Farcy;A. Arriordaz;S. Chéramy;F. Clermidy
在高性能计算的背景下，将更多的计算能力与通用核心或专用加速器集成起来，以用于人工智能(AI)应用，这提出了越来越多的挑战。由于先进节点的成本不断增加，以及缩小模拟和电路输入输出信号(IO)的难度，单芯片的替代架构解决方案正成为主流。使用3D技术的基于Chiplet的系统支持模块化和可扩展的架构和技术分区。然而，由于芯片集成在无源插入物上--硅或有机--仍然存在局限性。在这篇文章中，我们介绍了第一个CMOS有源插入器，集成了：1)无需任何外部元件的电源管理；2)实现任何芯片到芯片通信的分布式互连；以及3)系统基础设施、为测试而设计和电路IO。完整的电路原型集成了6个采用FDSOI 28 nm技术的芯片，这些芯片以65 nm工艺3D堆叠在这个有源插入器上，总共提供了96个计算核心。计算系统的完全可扩展性是使用创新的可扩展高速缓存相干存储器层次结构来实现的，该层次结构由分布式片上网络实现，具有3-Tit/S/mm高带宽3D-Plug接口，使用20-$u Ext{m}$节距微凸点，0.6 ns/mm低延迟异步互连，而六个芯片通过有源插入器以82%的峰值效率DC-DC转换器本地供电156 mW/mm2。通过对散热问题的研究，验证了该方法的可行性。
In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of advanced nodes and the difficulties of shrinking analog and circuit input output signals (IOs), alternative architecture solutions to single die are becoming mainstream. Chiplet-based systems using 3D technologies enable modular and scalable architecture and technology partitioning. Nevertheless, there are still limitations due to chiplet integration on passive interposers—silicon or organic. In this article we present the first CMOS active interposer, integrating: 1) power management without any external components; 2) distributed interconnects enabling any chiplet-to-chiplet communication; and3) system infrastructure, design-for-test, and circuit IOs. The IntAct circuit prototype integrates six chiplets in FDSOI 28-nm technology, which are 3D-stacked onto this active interposer in 65-nm process, offering a total of 96 computing cores. Full scalability of the computing system is achieved using an innovative scalable cache-coherent memory hierarchy, enabled by distributed network-on-chips, with 3-Tbit/s/mm2 high bandwidth 3D-plug interfaces using 20- $mu ext{m}$ pitch micro-bumps, 0.6-ns/mm low latency asynchronous interconnects, while the six chiplets are locally power-supplied with 156-mW/mm2 at 82%-peak-efficiency dc–dc converters through the active interposer. Thermal dissipation is studied showing the feasibility of such approach.