A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC
A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC
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基于 3D-IC NoC 的 MPSoC 中的 0.9 pJ/bit、12.8 GByte/s WideIO 存储器接口
DOI：
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发表时间：
2013
期刊：
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通讯作者：
J. Michailos
中科院分区：
文献类型：
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作者：
D. Dutoit;C. Bernard;S. Chéramy;F. Clermidy;Y. Thonnart;P. Vivet;Christian Freund;Vincent Guerin;Stephane Guilhot;S. Lecomte;Gianni Qualizza;J. Pruvost;Y. Dodo;Nicolas Hotelier;J. Michailos
3D集成电路（3D-IC）为改善管芯之间的SoC到存储器互连带宽提供了架构机会。提出了一种基于片上网络的多芯片片上系统（MPSoC）和多通道WideIO移动的SDRAM的两层3D-IC设计方案。3D-IC的测量结果表明，在最坏情况下可实现12.8 GByte/s的目标带宽，同时提供0.9 pJ/bit的3D I/O链路功率效率。
3D Integrated Circuit (3D-IC) opens architecture opportunities for improved SoC-to-memory interconnect bandwidth between dies. This paper presents the design of a two-tier 3D-IC composed of one NoC-based MPSoC and one multi-channel WideIO mobile SDRAM stacked in a face-to-back configuration. Measurements of the 3D-IC show that the targeted 12.8 GByte/s bandwidth is achieved in worst case conditions, while offering a 0.9 pJ/bit 3D I/O link power efficiency.