A 0.7-V 870-$\mu$ W Digital-Audio CMOS Sigma-Delta Modulator
A 0.7-V 870-$\mu$ W Digital-Audio CMOS Sigma-Delta Modulator
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DOI：
10.1109/jssc.2009.2014708
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发表时间：
2009-03
影响因子：
5.4
通讯作者：
Hyunsik Park;KiYoung Nam;D. Su;K. Vleugels;B. Wooley
中科院分区：
文献类型：
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作者：
Hyunsik Park;KiYoung Nam;D. Su;K. Vleugels;B. Wooley
介绍了一种高功耗、斩波稳定的开关电容Sigma-Delta(SigmaDelta)调制器，它结合了延迟输入前馈和单比较器跟踪多位量化，以实现高精度、低电压的模数(A/D)转换。所提出的结构的实验原型已经集成在0.18微米的CMOS工艺中。该样机工作在0.7V的电源电压下，采样率为5 MSamples/s，总功耗仅为870 MUW。对于25 kHz的信号带宽，该转换器的动态范围为100分贝，峰值信噪比(SNR)为100分贝，峰值信噪比(SNDR)为95分贝。
This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta (SigmaDelta) modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (A/D) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-mum CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870 muW of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.