FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach
FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach
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DOI：
10.1109/fpl.2006.311240
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发表时间：
2006-08
期刊：
影响因子：
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通讯作者：
K. Turkington;K. Masselos;G. Constantinides;P. Leong
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文献类型：
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作者：
K. Turkington;K. Masselos;G. Constantinides;P. Leong
由于其不断增加的资源密度，现场可编程门阵列（FPGA）已经能够有效地实现涉及浮点计算的大规模科学应用。在本文中FPGA相比，高端微处理器的持续性能的流行的浮点CPU性能基准，即LINPACK 1000。一组翻译和优化步骤已被应用到转换的LINPACK基准的顺序C描述，单片存储器模型的基础上，到一个并行的Handel-C描述，利用多个可用的存储器资源上的现实可重构计算平台。实验结果表明，使用Handel-C编程的最新一代FPGA可以实现比微处理器高6倍的持续浮点性能，同时工作在低60倍的时钟频率下。转换应用的方式，可以推广，允许高效的编译方法映射到FPGA的高层次的描述。
Due to their increasing resource densities, field programmable gate arrays (FPGAs) have become capable of efficiently implementing large scale scientific applications involving floating point computations. In this paper FPGAs are compared to a high end microprocessor with respect to sustained performance for a popular floating point CPU performance benchmark, namely LINPACK 1000. A set of translation and optimization steps have been applied to transform a sequential C description of the LINPACK benchmark, based on a monolithic memory model, into a parallel Handel-C description that utilizes the plurality of memory resources available on a realistic reconfigurable computing platform. The experimental results show that the latest generation of FPGAs, programmed using Handel-C, can achieve a sustained floating point performance up to 6 times greater than the microprocessor while operating at a clock frequency that is 60 times lower. The transformations are applied in a way that could be generalized, allowing efficient compilation approaches for the mapping of high level descriptions onto FPGAs.