A Defect Tolerance Scheme for Nanotechnology Circuits
A Defect Tolerance Scheme for Nanotechnology Circuits
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DOI：
10.1109/tcsi.2007.907875
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发表时间：
2007-11
期刊：
影响因子：
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通讯作者：
Ahmad A. Al-Yamani;S. Ramsundar;D. Pradhan
中科院分区：
文献类型：
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作者：
Ahmad A. Al-Yamani;S. Ramsundar;D. Pradhan
基于光刻的集成电路制造在特征尺寸方面正迅速接近其极限。目前的替代方案是基于纳米技术的制造，它依赖于纳米管或纳米线的自组装。这样的过程有很高的缺陷率，可以使用精心设计的缺陷容忍技术来容忍。提出了一种基于重构的纳米技术开关缺陷容限算法。与最近发表的技术相比，该算法的平均开关密度提高了50%至100%。该算法在通过最小化错误拒绝来提高产量方面也是一致的，结果显示在大样本上。改进百分比取决于制造的开关尺寸和期望的无缺陷尺寸，效率的改进与开关尺寸成正比。
Lithography-based integrated circuit fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology-based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques. The algorithm is also consistent in improving the yield through minimizing false rejects as the results show over a large sample. The improvement percentage varies depending on the manufactured switch size and the desired defect-free size with the improvement in efficiency directly proportional to the size of the switch.