FPGA architecture for 3-D FDTD acceleration using open CL
FPGA architecture for 3-D FDTD acceleration using open CL
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DOI：
10.1109/piers.2016.7735734
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发表时间：
2016-08
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影响因子：
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通讯作者：
Hasitha Muthumala Waidyasooriya;M. Hariyama;Yasuo Ohtera
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文献类型：
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作者：
Hasitha Muthumala Waidyasooriya;M. Hariyama;Yasuo Ohtera
时域有限差分（FDTD）方法[1]广泛应用于电磁仿真。它是一个迭代过程，其中一次迭代中的计算使用其先前迭代的结果。由于迭代次数通常很大，FDTD计算需要大量的处理时间。另一方面，与同一迭代中的单元对应的大多数计算（除了边界上的单元）是完全相互独立的。因此，多核CPU和GPU都已经用于加速计算。然而，在每次迭代中访问外部存储器，使得处理速度受到外部存储器带宽的限制。
The finite difference time domain (FDTD) method [1] is widely used in electromagnetic simulations. It is an iterative process where the computations in one iteration use the results of its previous iterations. Since the number of iterations are usually very large, FDTD computation requires a large amount of processing time. One the other hand, most of the computations corresponding to the cells in the same iteration (apart from the cells on the boundaries) are completely independent of each other. Therefore, both multicore CPUs and GPUs are already used to accelerate the computation. However, the external memory is accessed in every iteration, so that the processing speed is restricted by the external memory bandwidth.