Self calibrating circuit design for variation tolerant VLSI systems
Self calibrating circuit design for variation tolerant VLSI systems
复制标题
用于容变 VLSI 系统的自校准电路设计
DOI：
10.1109/iolts.2005.63
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
K. Roy
中科院分区：
文献类型：
--
作者：
C. Kim;S. Hsu;R. Krishnamurthy;S. Borkar;K. Roy
随着技术扩展到纳米范围，漏电流增加和工艺变化加剧对动态电路性能和鲁棒性产生影响。本文介绍了一种自校准过程补偿动态（PCD）电路技术，以保持动态电路的性能优势，减少延迟和鲁棒性的变化。与传统设计相比，根据裸片泄漏进行优化编程的可变强度保持器可使性能提高10%，延迟变化减少35%，鲁棒性失效裸片数量减少5/spl倍。还提出了一种新的漏电流传感器的设计，可以检测泄漏的变化，并产生的PCD技术的保持器控制信号。所提出的6通道漏电流传感器能够从管芯的多个位置进行高分辨率的片上漏电流测量，从而节省测试成本并实现管芯到管芯和管芯内工艺补偿。基于测量的泄漏数据的结果显示，与现有的泄漏传感器设计相比，1.9-10.2/spl倍/更高的信噪比和对电源和P/N偏斜变化的降低的灵敏度。采用片上漏电流传感器的PCD技术，设计了一个2读2写端口的128 /spl次/32位寄存器堆，并在1.2V、90 nm双V CMOS工艺下制作了测试芯片。
Increasing leakage current and aggravating process variations are showing impact on dynamic circuit performance and robustness as technology scales into the nanometer regime. This paper describes a self-calibrating process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage enables 10% faster performance, 35% reduction in delay variation, and 5/spl times/ reduction in the number of robustness failing dies compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. The proposed 6-channel leakage current sensor enables high-resolution on-chip leakage measurements from multiple locations of a die, saving testing cost and realizing both die-to-die and within-die process compensation. Results based on measured leakage data show 1.9-10.2/spl times/ higher signal-to-noise ratio and reduced sensitivity to supply and P/N skew variations compared to prior leakage sensor designs. The PCD technique with the on-die leakage current sensor is applied to a 2-read, 2-write ported 128 /spl times/ 32b register file and a test chip is fabricated in 1.2V, 90nm dual-V, CMOS process.