RADAR: RET-aware detailed routing using fast lithography simulations
RADAR: RET-aware detailed routing using fast lithography simulations
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DOI：
10.1145/1065579.1065678
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发表时间：
2005-06
期刊：
影响因子：
--
通讯作者：
Joydeep Mitra;YU Peng;D. Pan
中科院分区：
文献类型：
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作者：
Joydeep Mitra;YU Peng;D. Pan
This paper attempts to reconcile the growing interdependency between nanometer lithography and physical design. We first introduce the concept of lithography hotspots and the edge placement error (EPE) map to measure the overall printability and manufacturing effort. We then adapt fast lithography simulation models to generate EPE map. Guided by the EPE map, we develop effective RET-aware detailed routing (RADAR) techniques that can handle full-chip capacity to enhance the overall printability while maintaining other design closure. RADAR is implemented in an industry strength detailed router, and tested using some 65nm designs. Our experimental results show that we can achieve up to 40% EPE reduction with reasonable CPU time.
