Archon: A modern controller for high performance astronomical CCDs

Archon: A modern controller for high performance astronomical CCDs
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Archon:高性能天文 CCD 的现代控制器

DOI:
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发表时间:
2014
期刊:
Astronomical Telescopes and Instrumentation
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通讯作者:
G. Bredthauer
G. Bredthauer
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文献类型:
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作者:
G. Bredthauer

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商业fpga和模拟ic的快速发展使得Archon,一种新型模块化高性能天文CCD控制器的开发成为可能。CCD输出由带差分交流耦合前置放大器的16位100mhz adc数字化。来自ADC的原始数据流可以与标准图像数据并行存储到三个板载512 MB帧缓冲区中。采用数字相关双采样计算像素值。在低像素率(< 1 MHz)下,通过平均每像素数百个ADC样本可以实现的动态范围可以超过16位,因此提供了每像素存储32位的选项。CCD时钟由14位100mhz dac产生。驱动时钟的脚本定时核心可以每10ns为每个时钟产生一个新的目标电压,并且时钟转换速率可以单独编程。CCD偏置来自16位dac,连续监测电压和电流,并按可定制的顺序上下电。控制器和主机之间的通信通过千兆以太网接口(光纤或铜线)进行。CCD配置由一个简单的文本文件指定。总之,这些功能简化了科学ccd的调优和调试,并支持ccd受限成像。我介绍了控制器架构的细节,CCD调谐的例子,以及单独控制器的测量性能数据(100 kHz时108 dB和1 MHz时98 dB的动态范围)以及与STA1600LN CCD结合使用的性能数据。
The rapid evolution of commercial FPGAs and analog ICs has enabled the development of Archon, a new modular high performance astronomical CCD controller. CCD outputs are digitized by 16-bit 100 MHz ADCs with differential AC-coupled preamplifiers. The raw data stream from an ADC can be stored in parallel with standard image data into three onboard 512 MB frame buffers. Pixel values are computed using digital correlated double sampling. At low pixel rates (< 1 MHz), the dynamic range achievable by averaging hundreds of ADC samples per pixel can exceed 16 bits, so an option to store 32 bits per pixel is provided. CCD clocks are generated by 14-bit 100 MHz DACs. The scripted timing core driving the clocks can generate a new target voltage for each clock every 10 ns, and the clock slew rates are individually programmable. CCD biases are derived from 16-bit DACs, are continuously monitored for voltage and current, and power up and down in a customizable sequence. Communication between the controller and a host computer occurs over a gigabit Ethernet interface (fiber or copper). A CCD configuration is specified by a simple text file. Together, these features simplify the tuning and debugging of scientific CCDs, and enable CCD-limited imaging. I present details of the controller architecture, examples of CCD tuning, and measured performance data of the controller alone (dynamic range of 108 dB at 100 kHz and 98 dB at 1 MHz) and in combination with an STA1600LN CCD.